Saturday, May 12, 2012

Re: [ vuZs.net ] please share CS501 current papers

CS501 – Advance Computer Architecture

MID TERM Paper

Fall Spring 2012

 

MID TERM Paper

Dated May 11,2012

Time 1 hour

Attempt by On Sara Aman Sara Aman" <saraaman03@gmail.com>, May 11, 2012 at 2:14 PM,

 

Which register holds the address of the next instruction to b executed in the processor?         2 marks

Answer:

PC holds the address of next instruction to b executed in the processor.

Write the main functions of the branch instruction?     2 marks

Answer:

1)      calculate the target address

2)      to evolutes the condition

 

Write the structural RTL for the following instruction for the uni- bus  path implementation? in ra,rc          3 marks

Answer:

 

steps

RTL

T0-T2

Instruction fetch

T3

io[2]

T4

R[ra]C

 

How exception may b generated write the difference between external and internal exceptions?     3 marks

Answer:

 

Anything that interrupts the normal flow of execution of instructions in the

processor is called an exception.

• Exceptions may be generated by an external or internal event such as a mouse

click or an attempt to divide by zero etc.

• External exceptions or interrupts are generally asynchronous (do not depend on

the system clock) while internal exceptions are synchronous (paced by internal clock.

 

Write the two ways to increase the number of instruction in a given time by the processor? Explain each one briefly?  5 marks

 

Answer:

 

There are two ways to increase the number of instructions executed in a given time by a

processor

By increasing the clock speed

By increasing the number of instructions that can execute in parallel

Increasing the clock speed

• Increasing the clock speed is an IC design issue and depends on the advancements in

chip technology.

• The computer architect or logic designer can not thus manipulate clock speeds to

increase the throughput of the processor.

Increasing parallel execution of instructions

The computer architect cannot increase the clock speed of a microprocessor however

he/she can increase the number of instructions processed per unit time. In pipelining we

discussed that a number of instructions are executed in a staggered fashion, i.e. various

instructions are simultaneously executing in different segments of the pipeline. Taking

this concept a step further we have multiple data paths hence multiple pipelines can

execute simultaneously.

 

Write the structural RTL for the call instruction for the uni data path implementation?

Call ra, rab

Answer:

 

 

steps

RTL

T0-T2

Instruction fetch

T3

C PC

T4

T5

T6

 R[ra] C

CR[rb]

PCC

 

MID TERM Paper

Dated May 11,2012

Time 1 hour

Attempt by On Nauman Khalid, May 11, 2012 at 5:47 PM,

 Almost 70% MCQ's was from old Papers and quiz's

 

Subjective Part

 

Q -   Write a structural RTL for Shift instruction for Uni-Bus data path implementation.         shiftr ra, rb, c1     [5 Marks]                                                                                         

Q -  Write down one Advantage and Disadvantage of Microprogramming?   [3 Marks]

Q -  Difference between Memory Address Register and Memory Buffer Register?   [2 Marks]

Q -  4-5 instructions were given and asked the pipe-lining hazards in it also correct it.?  [2 Marks]

Q -  One Structural RTL Table was given, you have to tell the simple Equation and what is it for?   [5 Marks]

 

MID TERM Paper

Dated May 11,2012

Time 1 hour

Attempt by On syeda Areeba, May 11, 2012 at 5:47 PM,

Which registers hold the instructions that is being executed?(2 Marks)

What do you understand by the machine exceptions?(2 Marks)

Write the structural RTL for the mov immediate instruction for the mov immediate instruction for uni-bus data path implementation

Movi ra,c2 (3marks)

What is NOP instruction and its significance in pipelining? (3 Makrs)

Consider the following sequence of the instructions giving through the pipelined version of SRC

200:shl r6,r3,5

204:str r7,30

208:sub r2,r4,r5

2012:add r1,r2,r3

216:id r7,48

Idetify the hazards in these instructions. Also discuss how hazards be resolved (5 marks)

6.Write the structure RTL description for the uni-bus data path implementation

Jump[ra+2] (5 Marks)  

 

 


On Fri, May 11, 2012 at 9:32 PM, Safeena Ali <bc090403002@vu.edu.pk> wrote:

Assalam-o-Alaikum Frndz!
please share CS501 current papers
n solved past paperz



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